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[VHDL-FPGA-Verilog] Synthesizable_FIFO_verilog

Description: Synthesizable FIFO Model This example describes a synthesizable implementation of a FIFO. The FIFO depth and FIFO width in bits can be modified by simply changing the value of two parameters, `FWIDTH and `FDEPTH. For this example, the FIFO depth is 4 and the FIFO width is 32 bits.
Platform: | Size: 16384 | Author: lianlianmao | Hits:

[VHDL-FPGA-Verilog] generic_fifos.tar

Description: Generic FIFO, writen in verilog hdl
Platform: | Size: 12288 | Author: marco | Hits:

[USB develop] async_fifo2_corrected

Description: FIFO的部分verilog代码，其余部分我会陆续上传，-FIFO part of Verilog code, I will continue the rest of the upload,
Platform: | Size: 136192 | Author: | Hits:

[VHDL-FPGA-Verilog] Verilog_FIFO_ram

Description: 一个可以综合的Verilog 写的FIFO存储器，word格式-An integrated Verilog wrote FIFO memory, word format
Platform: | Size: 19456 | Author: hjx | Hits:

[VHDL-FPGA-Verilog] fifo_VHDL

Description: FIFO的源代码，详细描述FIFO的工作原理和过程，用VHDL编写。-FIFO of the source code, a detailed description of the work of FIFO principle and process of preparation with VHDL.
Platform: | Size: 9216 | Author: 胡志敏 | Hits:

[OS Develop] dfifo

Description: verilog，异步一进一出的例子，空满的标志。-verilog, into an asynchronous one example, air-filled logo.
Platform: | Size: 2048 | Author: 陈虎 | Hits:

[VHDL-FPGA-Verilog] zzmodelsim

Description: verilog仿真工具modelsim的使用教程,幻灯片形式的,图文并茂,简单易学.经典的老教材-ModelSim Verilog simulation tool use tutorials, slide the form of illustrations, easy to learn. classic old material
Platform: | Size: 505856 | Author: oasis | Hits:

[SCM] IA4420FIFO(C51)

Description: IA4420的FIFO操作源代码，是c51语言写的，不过移植起来很容易。-IA4420 the FIFO operation source code is written in C51 language, but the transplant is easy.
Platform: | Size: 1024 | Author: 刘先生 | Hits:

[OS Develop] FIFO

Description: 一个异步的FIFO的VERILOG程序,有测试程序-An asynchronous FIFO in Verilog procedures, test procedures have
Platform: | Size: 4096 | Author: 陈强 | Hits:

[VHDL-FPGA-Verilog] 37724082FIFO

Description: 基于Verilog HDL的异步FIFO设计与实现-Verilog HDL-based Asynchronous FIFO Design and Implementation
Platform: | Size: 3072 | Author: 汤奥 | Hits:

[VHDL-FPGA-Verilog] an_dcfifo_top_restored

Description: alteral FPGA VERILOG 利用 ROM DCFIFO 和RAM 实现高速到低速时钟域的数据传输 ，值得学习。-alteral FPGA VERILOG using ROM DCFIFO and RAM to realize high-speed low-speed clock domain data transfer, it is worth learning.
Platform: | Size: 928768 | Author: alison | Hits:

[VHDL-FPGA-Verilog] 68013FIFOIN

Description: Verilog HDL 编写的CY7C68013 SLAVE FIFO接口程序，实际测试可用。可以直接跟上位机连接，传输数据。-Verilog HDL prepared CY7C68013 SLAVE FIFO interface program, the actual test can be used. Keep pace with the digital machine can be directly connected to transmit data.
Platform: | Size: 664576 | Author: huanghui | Hits:

[VHDL-FPGA-Verilog] asynchronous-FIFO-structure

Description:
Platform: | Size: 545792 | Author: john | Hits:

[Graph Recognize] lcd-code

Description: 比较完整的LCD接口代码，verilog编写，分为6800和8080两种CPU接口，且有完整的仿真程序-Relatively complete LCD interface code, verilog prepared 6800 and 8080 is divided into two types of CPU interfaces, and there is a complete simulation program
Platform: | Size: 1831936 | Author: 李佳 | Hits:

[OS Develop] asyn_fifo

Description: verilog编写的异步fifo源代码，asyn_fifo.v为顶层，调用其他四个文件-asynchronous fifo prepared Verilog source code, asyn_fifo.v for top-level, call the other four documents
Platform: | Size: 2048 | Author: nihao | Hits:

[VHDL-FPGA-Verilog] FIFO

Description: 用VERILOG写的FIFO程序，可以直接引用经本人测试-VERILOG written using FIFO procedures, can be directly invoked by the I test
Platform: | Size: 1125376 | Author: 李俭 | Hits:

[VHDL-FPGA-Verilog] AS_FIFO_DESIGN_Verilog

Description: 使用Verilog硬件描述语言完成了一个异步FIFO的设计，供相关硬件开发人员参考。-Verilog hardware description language used to complete an asynchronous FIFO design, hardware development for the relevant reference.
Platform: | Size: 3072 | Author: 小米 | Hits:

[Embeded-SCM Develop] FIFO64

Description: FIFO级联，利用verilog语言实现Xilinx FIFO18单元的多个级联，增大FIFO深度。-FIFO cascade, using Verilog Xilinx FIFO18 language to achieve a number of cascade units, increasing the FIFO depth.
Platform: | Size: 3072 | Author: blackmew | Hits:

[VHDL-FPGA-Verilog] fifo_src

Description: verilog语言实现，利用BlockRAM实现FIFO。-Verilog language, the use of BlockRAM achieve FIFO.
Platform: | Size: 3072 | Author: blackmew | Hits:

[VHDL-FPGA-Verilog] FIFO_2

Description: VERILOG Synchronous FIFO. 4 x 16 bit words.-VERILOGSynchronous FIFO. 4 x 16 bit words.
Platform: | Size: 2048 | Author: likui | Hits:
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